The 8255 is a programmable, parallel I/O device simply called PPI.
It can be programmed to transfer data in various modes of I/O.
It provides 24 I/O pins that can be grouped into three 8 bit parallel ports: PORT A, PORT B and PORT C.
The 8 bits of port C is separated into two 4-bit ports: PORT C UPPER (PC4-PC7) and PORT C LOWER (PC0-PC3) see the fig1.0.
Checkout 1.1: What is need of 8255 for I/O interfacing?
PIN Diagram and its description
82c55A is the high performance CMOS version of 8255 by Intersil Company. It is manufactured using a self-aligned silicon gate CMOS process. The IC available in DIP, CLCC, DLCC packages.
VCC: The +5V power supply pin. A 0.1mF capacitor between pins 26 and 7 is recommended for decoupling.
DATA BUS (D0-D7): The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A.
READ: This control signal enables the Read operation. When the signal is low, the microprocessor reads data from a selected I/O Port of the 8255.
WRITE: This control signal enables the write operation. When the signal goes low, microprocessor writes data into a selected I/O Port or control register.
ADDRESS (A0,A1): These input signals, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1.
PORT A (PA0-PA7): 8-bit input and output port.
PORT B (PB0-PB7): 8-bit input and output port.
PORT C (PC0 -PC7): 8-bit input and output port.
In the functional diagram two control groups, labeled group A control and group B control define how the three I/O ports operate. The upper 4 bits of PORT C along with PORT A are associated with group A control while the lower 4 bits of PORT C along with PORT B are associated with group B control.
Checkout 1.2: What is the need of grouping the ports in 8255?
There are two different operating modes for the 8255. These modes must be defined by the microprocessor writing program or control words of 8255.
1) Bit Set-Reset mode (BSR) : BSR mode is used to define the handshaking signals.
2) I/O mode: It is used for I/O data transfer.
Control Word Register
The 8255 may be operated in one of the two modes (BSR or I/O), by initializing D7 bit in Control word register. If bit D7=1, 8255 operate in I/O mode and the bits D6-D0 determines I/O operations in various modes. For example, in fig 1.4 the bits D2, D1, D0 determine the Group B control. Bit D2 is for I/O mode selection and bits D1 and D0 are used to initialize the ports as Input or output. Similarly the bits D6-D3 determines the Group A control. D6 and D5 bits are for mode selection and the bits D4 and D3 are used to initialize the ports as input or output see fig 1.4.
If bit D7=0, 8255 operates in BSR mode and the Port C bits are used to initialize handshaking signals.
Control word in I/O mode :
I/O Operating Modes
Mode 0: Simple Input or Output:
In this mode, ports A, B and C are used as simple 8-bit I/O ports. This mode doesn’t require handshaking signals. Hence no need of BSR mode. So we can directly program the control word to I/O mode.
Note: BSR mode is used to define the handshaking signals.
Note: The two halves of PORT C are independent, so one half can be used as input, and other half used as output.
Fig 1.5 shows that control word is programmed as simple I/O mode or mode 0 by setting D7 = 1.
Mode 1: Strobed I/O or single Handshake I/O
This functional configuration provides a means for transferring I/O data to or from, a specified port in conjunction with strobes or “hand shaking” signals.
When Group A and Group B are programmed to mode1. The two ports operated in strobed I/O mode. To do this first of all the control word register is programmed to BSR mode to define the strobe signal as handshaking. After that again control word register is programmed to I/O.
Mode 1 Basic Function Definitions:
• Two Groups (Group A and Group B)
• Each group contains one 8-bit port and one 4-bit control/data port
• The 8-bit data port can be either input or output. Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit port.
Group A and B as input in mode1:
Input control signal Definition
STB (Strobe Input)
A Logic low on this input loads data into the port from external peripheral device.
IBF (Input Buffer Full)
Logic high on this output indicates to the peripheral device that the data has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB input being low and is reset by the rising edge of the RD input.
INTR (Interrupt Request)
INTR is a signal used to indicate the microprocessor, that a byte has been received on 8255 port. Now the microprocessor collects the data byte from the 8255 port.
INTR is set by the condition: STB == 1, IBF == 1 and INTE == 1. It is reset by the falling edge of RD.
Group A and B as output in mode1:
Output control signal Definition:
OBF (Output Buffer Full):
The logic low on this signal is an indication to the peripheral device that the microprocessor written a data byte into the 8255 port.
ACK (Acknowledge input):
After receiving OBF signal, the peripheral sends ACK signal as low to 8255 indicating that it is ready to accept the data.
INTR (Interrupt request):
Logic high on this output can be used to interrupt the microprocessor when an output device has accepted data transmitted by the microprocessor. INTR is set when ACK == 1, OBF == 1 and INTE == 1. It is reset by the falling edge of WR.
Mode 2 (Bi-Directional handshaking I/O):
This mode is used primarily in applications such as data transfer between two computers. In this mode, PORT A can be configured as the bidirectional port and PORT B either in Mode0 or Mode1. PORT A uses five signals from PORT C as handshake signals for data transfer. The remaining three signals from PORT C can be used either as simple I/O or as handshake for port B.
Bi-Directional Bus I/O Control Signal Definition
OBF (Output Buffer Full). The logic low on this signal is an indication to the peripheral device that the microprocessor written a data byte into the 8255 port.
ACK (Acknowledge). After receiving OBF signal, the peripheral sends ACK signal as low to 8255 indicating that it is ready to accept the data .
INTE1 (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4 as shown in fig 1.8.
STB (Strobe Input): A Logic low on this input loads data into the port from external peripheral device.
IBF (Input Buffer full): Logic high on this output indicates to the peripheral device that the data has been loaded into the 8255 port (i.e., Ack to peripheral device). IBF is set by STB input being low and is reset by the rising edge of the RD input.
INTE 2 (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4 as shown in fig 1.8 .
INTR (Interrupt Request): A high on this output can be used to interrupt the microprocessor for both input or output operations.
Setting/Resetting PORT C bits as handshaking signal in BSR mode:
Checkout 1.0: What is need of 8255 for I/O interfacing?
Answer: There are two reasons for using 8255 between 8086 and I/O devices.
1) To achieve Speed compatibility between high speed microprocessor and slow I/O devices.
2) Reducing hardware complexity by interfacing the I/O devices through program.
Reason 1: Let us consider a keyboard interfaced serially to 8086 microprocessor as shown in Fig. In this example, the keyboard interface is not drawn with bunch of signal connections. It is simply drawn to make the reader understand the concept easily and get an idea about the use of 8255 (PPI).
In the Fig 1.a, microprocessor receives ASCII code of a key serially, which is sent from keyboard after the key hit. Here keyboard is mechanical device on which a user can type characters at rate up to 130 words per minute and microprocessor is high speed semiconductor device, which accept and process millions of words per second.. There is no speed compatibility between these two devices. To achieve the speed compatibility, place a semiconductor bidirectional buffer (called as port in 8255 ) (synchronize the buffer and microprocessor) between microprocessor and keyboard.
When key is hit, the ASCII code of the key transferred to buffer serially. If the buffer is full, then it intimates the microprocessor through a separate signal (IBF) that it has received a key. Now the microprocessor collects the entire 8-bit data by reading buffer. In this way, speed compatibility is achieved. There are three programmable ports are available in 8255.
Reason 2: microcomputer is used for general purpose; so that many devices are interfaced to microprocessor. For example, keyboard, mouse, printer, monitor, Hard drive, etc., To interface all these devices to microprocessor require more buffers and I/O lines, which increases the circuit complexity and space occupied.
This can be solved by controlling fixed number of buffers or PORTs programmatically.
8255 PPI has three bi-directional I/O PORTs (labeled A, B, C). These ports are programmed as input/output using control word register and interface many devices using time share basis using these fixed ports.
Checkout 1.2: What is the need of grouping the ports in 8255?
Answer: Generally, the I/O devices are connected to 8255 are different types like Led, keyboard, mouse, disk drive, ADC, DAC, Stepper motor, DC motor, Serial bidirectional data transfer between microprocessors, etc.
All these I/O devices are categorized into three modes.
1) Simple I/O mode: It is the basic I/O mode, where the processor simply sends the data to output device. The processor doesn’t care about the data sent has been received or not by the device. For example, consider 8255 is driving a led, connected to one of the output ports. Here, 8255 simply sends logic high to glow an Led. But it doesn’t care about the signal reached to Led or not.
2) Strobe I/O mode: In many I/O applications, valid data present on an external device only at certain time, so it must be read in at that time. For example, when a key is pressed on the keyboard. It sends out the ASCII code for the pressed key on eight parallel data lines, and also sends out a strobe signal on another line to indicate that valid data present on the eight data lines.
3) Bidirectional Handshaking I/O mode: Many I/O devices cannot accept data at an arbitrary rate. Using status bits to indicate that a device is ready to accept or transmit data is known as handshaking. It gets this name because the protocol is similar to two people agreeing on some method of transfer by a hand shake.
Ex: Serial data transfer between two devices.
To support all these different I/O the 8255 ports are categorized as two groups (group A and group B).